Processing-in-memory Accelerators Toward Energy-Efficient Real-World Machine Learning

Abstract: Unlike the sensational evolution of machine learning, hardware development falls far behind because of the inefficiency across the separation of storage and computation. Processing-in-memory (PIM) accelerators have appeared to overcome the stagnant progress in hardware by infusing the processing capability into memories. PIM designers should consider various factors from bottom to top and horizontally to establish high efficiency of reliable hardware.

In this talk, I will explain energy-efficient PIM-based circuit, architecture, and system designs with diverse memory types to accelerate machine learning algorithms. Specifically, I will start from 1) PIM designs at low levels of devices and circuits for deep learning models, specifically with resistive random-access memory (RRAM), a representative emerging nonvolatile memory (eNVM). After discussing the device and circuits for 3D architecture potential specifically, I will elevate to higher levels of architecture and systems to unveil the importance of dataflow in PIM accelerators. 2) I will introduce a first-of-its-kind systemic paradigm, input-stationary dataflow, implemented in a novel 3D architecture. The effectiveness of the input-stationary dataflow will be demonstrated through its application to a fabricated SRAM-PIM chip implementable to seizure patients for diagnosis automation. Likewise, 3) I will suggest directions of PIM designs at the utmost level of algorithms and applications in our machine-learning ubiquitous lives, finally emphasizing privacy protection in machine learning with a DRAM-PIM accelerator. This talk will highlight that PIM technology is leveraged in a wide range of domains and applications on a machine-learning basis to achieve exceptional performance and efficiency.

Processing-in-memory Accelerators Toward Energy-Efficient Real-World Machine Learning

Abstract: Unlike the sensational evolution of machine learning, hardware development falls far behind because of the inefficiency across the separation of storage and computation. Processing-in-memory (PIM) accelerators have appeared to overcome the stagnant progress in hardware by infusing the processing capability into memories. PIM designers should consider various factors from bottom to top and horizontally to establish high efficiency of reliable hardware.

In this talk, I will explain energy-efficient PIM-based circuit, architecture, and system designs with diverse memory types to accelerate machine learning algorithms. Specifically, I will start from 1) PIM designs at low levels of devices and circuits for deep learning models, specifically with resistive random-access memory (RRAM), a representative emerging nonvolatile memory (eNVM). After discussing the device and circuits for 3D architecture potential specifically, I will elevate to higher levels of architecture and systems to unveil the importance of dataflow in PIM accelerators. 2) I will introduce a first-of-its-kind systemic paradigm, input-stationary dataflow, implemented in a novel 3D architecture. The effectiveness of the input-stationary dataflow will be demonstrated through its application to a fabricated SRAM-PIM chip implementable to seizure patients for diagnosis automation. Likewise, 3) I will suggest directions of PIM designs at the utmost level of algorithms and applications in our machine-learning ubiquitous lives, finally emphasizing privacy protection in machine learning with a DRAM-PIM accelerator. This talk will highlight that PIM technology is leveraged in a wide range of domains and applications on a machine-learning basis to achieve exceptional performance and efficiency.