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Enhancing FPGA Synthesis for Space Applications:Performance Evaluation of ScaleHLS in the ADAPT Project
Abstract: This thesis investigates the application of ScaleHLS, a high-level synthesis (HLS) tool, for optimizing Field-Programmable Gate Array (FPGA) synthesis in space applications, with a focus on the Advanced Particle-astrophysics Telescope (ADAPT) project. The work explores the transformation of C code into FPGA-compatible designs using ScaleHLS, aiming to enhance computational efficiency and resource utilization.
Initially, the study delves into the architectural nuances of ADAPT, highlighting the significance of efficient data processing in space-adaptive instruments. Subsequently, it presents a detailed methodology for adapting and optimizing the ADAPT project's algorithms through ScaleHLS, demonstrating the tool's impact on simplifying the code-to-hardware translation process. The thesis culminates in a performance evaluation, analyzing resource utilization and computational speed to quantify the enhancements ScaleHLS brings to FPGA synthesis for space applications. This research not only underscores the efficacy of ScaleHLS in optimizing hardware design but also establishes a foundation for future advancements in high-level synthesis, fostering the development of more efficient space-oriented computational systems.
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Enhancing FPGA Synthesis for Space Applications:Performance Evaluation of ScaleHLS in the ADAPT Project
Abstract: This thesis investigates the application of ScaleHLS, a high-level synthesis (HLS) tool, for optimizing Field-Programmable Gate Array (FPGA) synthesis in space applications, with a focus on the Advanced Particle-astrophysics Telescope (ADAPT) project. The work explores the transformation of C code into FPGA-compatible designs using ScaleHLS, aiming to enhance computational efficiency and resource utilization.
Initially, the study delves into the architectural nuances of ADAPT, highlighting the significance of efficient data processing in space-adaptive instruments. Subsequently, it presents a detailed methodology for adapting and optimizing the ADAPT project's algorithms through ScaleHLS, demonstrating the tool's impact on simplifying the code-to-hardware translation process. The thesis culminates in a performance evaluation, analyzing resource utilization and computational speed to quantify the enhancements ScaleHLS brings to FPGA synthesis for space applications. This research not only underscores the efficacy of ScaleHLS in optimizing hardware design but also establishes a foundation for future advancements in high-level synthesis, fostering the development of more efficient space-oriented computational systems.