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Assembly Series

A tradition of convening thought leaders since 1953

McKelvey School of Engineering

Brown School

Computer System Architecture Pipelining

Monday, April 8 | 3:00 PM - 4:00 PM

McKelvey Hall, McKelvey 1020

Michael Hall
Software Engineer
OpenVault

Pipelining is a fundamental and essential architectural technique in computer systems for achieving high performance. In this talk, we will begin by exploring single-cycle and multi-cycle architecture designs. Since programs consist of billions of instructions to be executed, optimizing for high throughput rather than low instruction latency becomes important for making programs faster. This is the motivation for a pipelined architecture. We will introduce the pipelined architecture and demonstrate how it enhances performance. Additionally, we will discuss the dependencies and hazards inherent in pipeline designs, along with the basics of how to handle them.


Talk Location: McKelvey 1020

Event Type

Seminar/Colloquia

Schools

McKelvey School of Engineering

Topic

Science & Technology

Website

https://cse.wustl.edu/news-events/col...

Department
Computer Science & Engineering
Event Contact

cody.copeland@wustl.edu

Speaker Information

Dr. Michael Hall received a B.S. degree in Computer Engineering and an M.S. degree in Electrical Engineering from Southern Illinois University Edwardsville. He subsequently obtained a Ph.D. in Computer Engineering from Washington University in St. Louis. He has been employed in industry for approximately 9 years as a Software Engineer, currently at OpenVault. His experience spans DOCSIS networking, backend software engineering, parallel programming, optimization, and data science. Additionally, he serves as an Adjunct Instructor in the Computer Science and Engineering Department at Washington University in St. Louis, teaching evening classes. Dr. Hall has also collaborated with Hailey Hall on editing and publishing a children's book. His research interests include performance analysis, modeling, digital systems, and reconfigurable logic.

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